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VerilogHDL_Emample
- 其他说明: 文中实例基本都不依赖实际具体的硬件,可以在任何厂家任何系列的FPGA/CPLD下综合使用(如Altera等,只要资源充足),还可以利用Synoposy公司的工艺库影射到ASIC,完全可以当作软IPCore使用。 -Other notes: the text does not rely on practical and concrete examples of basic hardware, manufacturers of any series in any of the
code
- 《EDA技术》课程是一门实用性较强、涉及面较广的专业课,它不仅是电子信息类专业本科学生的必修课,也是电子学、计算机与自动控制类专业的重要专业选修课。它是硬件电子电路设计领域的基础课程之一,是《FPGA设计》、《ASIC设计》等课程的先修课。-" EDA Technology" course is a practical, strong and covers a broader courses, electronic information is not only a requi
asic_study
- 压缩包中是ASCI学习资料,包括一个台湾中山大学ASIC实验室综合脚本教程,一本springer出版的交大家用system verilog做验证的书,还有一个xilinx论证的XAPP726 - 无线基站基带处理应用中的FPGA的理由。对大家做通信后端设计很有帮助。-ASCI is compressed package learning materials, including a laboratory in Taiwan Sun Yat-ASIC synthesis scr ipts tuto
C-Embedded-Processor
- Costumizable Embedded Processor, design processor in hdl for asic or fpga
EDK_lab_chinese
- Almighty-EDK开发套件是一款以Xilinx最新90ns工艺的Spartan3S700A FPGA为核心,以 USB2.0及RJ45,VGA,AC97接口应用为主要针对市场的产品,利用Almighty开发板上的高效低成 本ADC及FPGA外围大容量SDR SDRAM、Nor Flash存储器,配合使用FPGA内部的乘法器单元、 逻辑单元及MicroBlaze软核处理器,用户可以搭建强大的SOC应用平台,同时Almighty开发套件支 持通过USB2.0/RS232等PC接
ip_core
- 一些FPGA上用的到的IP核,种类非常全,开发小的ASIC基本上够用了-To use some of the FPGA IP cores, species are very full, the development of ASIC basically small enough
interpolation-filer-rtl
- synthesizable verilog rtl implemetation of interpolation filter, for both asic and fpga. 64x interpolation. interp_filter.v interp_first.v interp_second.v interp_third.v upsample.v
science-1
- FPGA versus ASIC Comparison
JointwaveE440
- H.264 1080p60 FPGA/ASIC设计方案-H.264 1080p60 FPGA/ASIC
JointwaveE460
- jointwave公司的h264编码方案,可实现1080P30,运用在FPGA/ASIC设计-jointwave h264 encoding scheme can be realized 1080P30, the use of FPGA/ASIC design
Copy-of-DIGITAL-VLSI-DESIGN
- a manual for design implementation of fpga and ASIC using verilog
Example-8-1
- 我的观点是Verilog和VHDL对于高手而言各有利弊,Verilog感觉更适合于RTL(寄存器传输级)的描述,而VHDL更适于System级的建模。 但是初学者强烈建议学习Verilog,更容易入手些,但是学习过程中一定要注意下面一点,毕竟国内外大公司现在大都采用Verilog是有其原因的。 l FPGA/CPLD、ASIC的逻辑设计所采用的硬件描述(HDL)语言是同软件语言(如C,C++等)是有本质区别的!虽然Verilog很多语法规则和C语言相似,但是Verilog是硬件描述
divider
- VERILOG编写的24位除法器代码核,是FPGA或者ASIC设计中的一核心计算模块。-VERILOG written 24 divider code nuclear FPGA or ASIC design in a core module.
sqrt
- VERILOG描述的开平方模块核,开方运算是FPGA或ASIC设计中所需要的核心运算模块。-VERILOG descr iption of open square modules nuclear root operation is the core computing module FPGA or ASIC design.
binBCD
- bcd码ASIC码的FPGA VHDL实现加仿真-bcd to ASIC in FPGA VHDL
sockit_owm_latest.tar
- 1-wire master written in Verilog HDL, ready for integration into a FPGA or ASIC based SoC. A port of the 1-wire Public Domain Kit (version 3.10r2) from Maxim is also provided, with all the code required for integration into the Altera development
A3P40_ProASIC3
- ProASIC3, the third-generation family of Actel flash FPGAs, offers performance, density, and features beyond those of the ProASICPLUS® family. Nonvolatile flash technology gives ProASIC3 devices the advantage of being a secure, low-power, sing
Verilog_HDl
- Verilog HDL是一种硬件描述语言(HDL:Hardware Discr iption Language),是一种以文本形式来描述数字系统硬件的结构和行为的语言,用它可以表示逻辑电路图、逻辑表达式,还可以表示数字逻辑系统所完成的逻辑功能。 -VHDL language is a high-level language for circuit design, digital systems primarily used to describe the structure, behavior,
VLSI-Project-Median-filer
- FPGA和ASIC实现的图像中值滤波模块,各模块的仿真结果以及MATLAB,Modelsim联合仿真。这是中科大超大规模集成电路设计优化的final project。附有最终版的report和presention。-FPGA and ASIC implementation of image filtering modules, each module of the simulation results and MATLAB, Modelsim co-simulation. This is the
CPU
- 基于FPGA控制的ASIC CPU系统设计,全是用VERILOG代码编写,可以做加减乘除运算 -FPGA-based control ASIC CPU system design, all made with VERILOG code writing, arithmetic operations can be done